Through-Silicon Vias for 3D Integration
by: John H. Lau, Ph.D.
Abstract: A comprehensive guide to TSV and other enabling technologies for 3D integration. Written by an expert with more than 30 years of experience in the electronics industry, Through-Silicon Vias for 3D Integration provides cutting-edge information on TSV, wafer thinning, thin-wafer handling, microbumping and assembly, and thermal management technologies. Applications to high-performance, high-density, low-power-consumption, wide-bandwidth, and small-form-factor electronic products are discussed. This book offers a timely summary of progress in all aspects of this fascinating field for professionals active in 3D integration research and development, those who wish to master 3D integration problem-solving methods, and anyone in need of a low-power, wide-bandwidth design and high-yield manufacturing process for interconnect systems. Coverage includes: • Nanotechnology and 3D integration for the semiconductor industry • TSV etching, dielectric-, barrier-, and seed-layer deposition, Cu plating, CMP, and Cu revealing • TSVs: mechanical, thermal, and electrical behaviors • Thin-wafer strength measurement • Wafer thinning and thin-wafer handling • Microbumping, assembly, and reliability • Microbump electromigration • Transient liquid-phase bonding: C2C, C2W, and W2W • 2.5D IC integration with interposers • 3D IC integration with interposers • Thermal management of 3D IC integration • 3D IC packaging
Full details
Table of Contents
- A. About the Author
- B. Foreword
- C. Preface
- D. Acknowledgments
- 1. Nanotechnology and 3D Integration for the Semiconductor Industry
- 2. Through-Silicon Via Technology
- 3. Through-Silicon Vias: Mechanical, Thermal, and Electrical Behaviors
- 4. Thin-Wafer Strength Measurement
- 5. Thin-Wafer Handling
- 6. Microbumping, Assembly, and Reliability
- 7. Microbump Electromigration
- 8. Transient Liquid-Phase Bonding: Chip-to-Chip, Chip-to-Wafer, and Wafer-to-Wafer
- 9. Thermal Management of Three-Dimensional Integrated Circuit Integration
- 10. Three-Dimensional Integrated Circuit Packaging
- 11. Future Trends of 3D Integration
Tools & Media
Expanded Table of Contents
- A. About the Author
- B. Foreword
- C. Preface
- D. Acknowledgments
- 1. Nanotechnology and 3D Integration for the Semiconductor Industry
- Introduction
- Nanotechnology
- Three-Dimensional Integration
- Challenges and Outlook of 3D Si Integration
- Potential Applications and Challenges of 3D IC Integration
- Recent Advances of 2.5D IC Integration (Interposers)
- New Trends in TSV Passive Interposers for 3D IC Integration
- Embedded 3D IC Integration
- Summary and Recommendations
- TSV Patents
- References
- General Readings
- 2. Through-Silicon Via Technology
- Introduction
- Who Invented TSV and When
- High-Volume Products with TSV Technology
- Via Forming
- Dielectric Isolation Layer (Oxide Liner) Deposition
- Barrier (Adhesion) Layer and Seed (Metal) Layer Deposition
- TSV Filling by Cu Plating
- Chemical-Mechanical Polishing of Cu Plating Residues
- TSV Cu Reveal
- FEOL and BEOL
- TSV Processes
- References
- 3. Through-Silicon Vias: Mechanical, Thermal, and Electrical Behaviors
- 4. Thin-Wafer Strength Measurement
- 5. Thin-Wafer Handling
- Introduction
- Wafer Thinning and Thin-Wafer Handling
- Adhesive Is the Key
- Thin-Wafer Handling Issues and Potential Solutions
- Effect of Dicing Tape on Thin-Wafer Handling of Wafers with Cu/Au Pads
- Effect of Dicing Tape on Thin-Wafer Handling of Wafers with Cu-Ni-Au UBMs
- Effect of Dicing Tape on Thin-Wafer Handling of Interposer with RDLs and Ordinary Solder Bumps
- Materials and Equipments for Thin-Wafer Handling
- Adhesive and Process Guidelines for Thin-Wafer Handling
- Summary and Recommendations
- 3M Wafer Support System
- EVG's Temporary Bonding and Debonding System
- Thin-Wafer Handling with Carrierless Technology
- References
- 6. Microbumping, Assembly, and Reliability
- Introduction
- Problem Definition
- Electroplating Method for Wafer Bumping of Ordinary Solder Bumps
- Assembly of 3D IC Integration SiPs
- Electroplating Method for Wafer Bumping of Solder Microbumps
- Can We Apply the Same Parameters of the Electroplating Method for Ordinary Solder Bumps to Microbumps?
- Summary and Recommendations
- Lead-Free Fine-Pitch Solder Microbumping
- Lead-Free Fine-Pitch C2C Solder Microbump Assembly
- Wafer Bumping of Lead-Free Ultrafine-Pitch Solder Microbumps
- Conclusions and Recommendations
- References
- 7. Microbump Electromigration
- 8. Transient Liquid-Phase Bonding: Chip-to-Chip, Chip-to-Wafer, and Wafer-to-Wafer
- Introduction
- How Does Low-Temperature Bonding with Solder Work?
- Low-Temperature C2C [(SiO2/Si3N4/Ti/Cu) to (SiO2/Si3N4/Ti/Cu/In/Sn/Au)] Bonding
- Low-Temperature C2C [(SiO2/Ti/Cu/Au/Sn/In/ Sn/Au) to (SiO2/Ti/Cu/Sn/In/Sn/Au)] Bonding
- Low-Temperature C2W [(SiO2/Ti/Au/Sn/In/Au) to (SiO2/Ti/Au)] Bonding
- Low-Temperature W2W [TiCuTiAu to TiCuTiAuSnInSnInAu] Bonding
- References
- 9. Thermal Management of Three-Dimensional Integrated Circuit Integration
- Introduction
- Effects of TSV Interposer on Thermal Performance of 3D Integration SiPs
- Thermal Performance of 3D Memory-Chip Stacking
- Effect of Thickness of the TSV Chip on Its Hot-Spot Temperature
- Summary and Recommendations
- Thermal Management System with TSVs and Microchannels for 3D Integration SiPs
- References
- 10. Three-Dimensional Integrated Circuit Packaging
- Introduction
- Cost: TSV Technology versus Wire-Bonding Technology
- Wire Bonding of Stack Dies on Cu–Low-k Chips
- Bare Chip-to-Chip and Face-to-Face Interconnects
- Low-Cost, High-Performance, and High-Density SiPs with Face-to-Face Interconnects
- Fan-Out-Embedded WLP-to-Chip (Face-to-Face) Interconnects
- A Note on Wire-Bonding Reliability
- References
- 11. Future Trends of 3D Integration
Book Details
Title: Through-Silicon Vias for 3D Integration
Publisher: McGraw-Hill Education: New York, Chicago, San Francisco, Athens, London, Madrid, Mexico City, Milan, New Delhi, Singapore, Sydney, Toronto
Copyright / Pub. Date: 2013 McGraw-Hill Education
ISBN: 9780071785143
Authors:
John H. Lau, Ph.D.
has spent more than 30 years in the electronics industry, mainly at HP/Agilent, and currently serves as a fellow of the Industrial Technology Research Institute (ITRI) in Taiwan. He has authored or coauthored 17 books, including Reliability of RoHS-Compliant 2D and 3D IC Interconnects , Advanced MEMS Packaging, Electronics Manufacturing, and Low Cost Flip Chip Technologies.
Description: A comprehensive guide to TSV and other enabling technologies for 3D integration. Written by an expert with more than 30 years of experience in the electronics industry, Through-Silicon Vias for 3D Integration provides cutting-edge information on TSV, wafer thinning, thin-wafer handling, microbumping and assembly, and thermal management technologies. Applications to high-performance, high-density, low-power-consumption, wide-bandwidth, and small-form-factor electronic products are discussed. This book offers a timely summary of progress in all aspects of this fascinating field for professionals active in 3D integration research and development, those who wish to master 3D integration problem-solving methods, and anyone in need of a low-power, wide-bandwidth design and high-yield manufacturing process for interconnect systems. Coverage includes: • Nanotechnology and 3D integration for the semiconductor industry • TSV etching, dielectric-, barrier-, and seed-layer deposition, Cu plating, CMP, and Cu revealing • TSVs: mechanical, thermal, and electrical behaviors • Thin-wafer strength measurement • Wafer thinning and thin-wafer handling • Microbumping, assembly, and reliability • Microbump electromigration • Transient liquid-phase bonding: C2C, C2W, and W2W • 2.5D IC integration with interposers • 3D IC integration with interposers • Thermal management of 3D IC integration • 3D IC packaging
