Phase-Locked Loop Synthesizers


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Phase-Locked Loop Synthesizers
Phase-Locked Loop SynthesizersThe traditional synthesizer consists of a single loop and the step size of the output frequency is equal to the reference frequency at the phase detector. Figure 9.1 shows this classic approach.
Block diagram of a PLL synthesizer driven by a frequency standard, DDS, or fractional-<emphasis role="italic">N</emphasis> synthesizer for high resolution at the output. The last two standards allow a relatively low division ratio and provide quasi-arbitrary resolution.
Citation
Prof. Dr.-Ing. habil. Dr. h.c. mult. Ulrich L. Rohde; Jerry C. Whitaker; Hans Zahnd: Communications Receivers: Principles and Design, Fourth Edition. Phase-Locked Loop Synthesizers, Chapter (McGraw-Hill Professional, 2017), AccessEngineering Export