Noise and Performance Analysis of PLL Systems


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Noise and Performance Analysis of PLL Systems
Noise and Performance Analysis of PLL SystemsTo illustrate the effectiveness of CAD tools in PLL analysis, let us consider the design of a PLL synthesizer operating from 110 to 210 MHz. A reference frequency of 10 kHz is used, and the tuning diode has a capacitance range from 6 to 60 pF. For performance reasons we select a type 2 third-order loop. The phase calculations use Leeson's model [9.10] for oscillator noise and the following equation
Citation
Prof. Dr.-Ing. habil. Dr. h.c. mult. Ulrich L. Rohde; Jerry C. Whitaker; Hans Zahnd: Communications Receivers: Principles and Design, Fourth Edition. Noise and Performance Analysis of PLL Systems, Chapter (McGraw-Hill Professional, 2017), AccessEngineering Export