Adding an Existing IP to the Project


Please sign in to view the rest of this entry.

Adding an Existing IP to the Project
Adding an Existing IP to the ProjectWe can add an existing IP block to the project. The beauty of using IP blocks is that the HDL used for generating the IP is not important. In other words, we can use an IP generated by VHDL in a Verilog project or vice versa. Therefore, this option allows us merging Verilog and VHDL descriptions in the same project. Let's analyze how this can be done next.
Adding an Existing IP in Verilog Let's start with the custom-generated IP block in Sec. 4.7. There, we have generated the IP block for the first system in Verilog. Now, let's …
Citation
Cem √únsalan, Ph.D.; Bora Tar, Ph.D.: Digital System Design with FPGA: Implementation Using Verilog and VHDL. Adding an Existing IP to the Project, Chapter (McGraw-Hill Professional, 2017), AccessEngineering Export