Summary


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Summary
SummaryVerilog and VHDL are the HDLs to be used throughout the book. We explored the fundamental properties of both HDLs through examples in this chapter. Basically, we explored the module representation in Verilog. Then, we introduced three modeling methods related to it. Afterward, we considered the effect of timing and delays in modeling. We also considered hierarchical module representation in Verilog. We finally analyzed how a testbench can be formed in Verilog. We followed the same methodology in exploring VHDL fundamentals next. We also considered adding an IP block to a Verilog and VHDL project. Here, we benefit from the generated IP block for the first system in Sec. 4.7. In all these sectio…
Citation
Cem √únsalan, Ph.D.; Bora Tar, Ph.D.: Digital System Design with FPGA: Implementation Using Verilog and VHDL. Summary, Chapter (McGraw-Hill Professional, 2017), AccessEngineering Export