Synthesis


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Synthesis
1010608SynthesisOne of the best uses of VHDL today is to synthesize ASIC and FPGA devices. This chapter and the next focus on how to write VHDL for synthesis.Synthesis is an automatic method of converting a higher level of abstraction to a lower level of abstraction. There are several synthesis tools available currently, including commercial as well as university-developed tools. In this discussion, the examples use the commercially available Exemplar Logic Leonardo Sectrum synthesis tool.The current synthesis tools available today convert Regi…
Citation
Douglas L. Perry: VHDL : Programming By Example, Fourth Edition. Synthesis, Chapter (McGraw-Hill Professional, 2002), AccessEngineering Export