High-Level Design Flow


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High-Level Design Flow
1010608High-Level Design FlowThis chapter describes the design flow used to create complex FPGA and ASIC devices. The designer starts with a design specification, creates an RTL description, verifies that description, synthesizes the description to gates, uses place and route tools to implement the design in the chip, and then verifies that the final result is correct in terms of function and timing. The high-level design flow is shown in Figure 11-1.The first step in a high-leve…
Citation
Douglas L. Perry: VHDL : Programming By Example, Fourth Edition. High-Level Design Flow, Chapter (McGraw-Hill Professional, 2002), AccessEngineering Export