CPU: RTL Simulation


Please sign in to view the rest of this entry.

CPU: RTL Simulation
1010608CPU: RTL SimulationIn this chapter, a VHDL simulator is used to verify the functionality of the CPU VHDL RTL description. The VHDL RTL description of the CPU is simulated with a standard VHDL simulator to verify that the description is correct.A simulator needs two inputs: the description of the design and stimulus to drive the design. Sometimes designs are self-stimulating and do not need any external stimulus, but in most cases, VHDL designers use a VHDL testbench of one kind or another to drive the design being tested. The structure of the design looks like
Citation
Douglas L. Perry: VHDL : Programming By Example, Fourth Edition. CPU: RTL Simulation, Chapter (McGraw-Hill Professional, 2002), AccessEngineering Export