CPU: VITAL Simulation


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CPU: VITAL Simulation
1010608CPU: VITAL SimulationThe last step in the high-density FPGA design process is to run gate-level timing simulation of the design. Figure 17-1 shows the high-density FPGA design flow. The place and route process produces a number of files that need to be verified before the design is implemented. The gate-level timing simulation process verifies that the design from the place and route process is correct from a timing and functional point of view.Within VHDL, this process is …
Citation
Douglas L. Perry: VHDL : Programming By Example, Fourth Edition. CPU: VITAL Simulation, Chapter (McGraw-Hill Professional, 2002), AccessEngineering Export