At Speed Debugging Techniques


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At Speed Debugging Techniques
1010608At Speed Debugging TechniquesThroughout the book so far we have discussed a number of techniques for implementing VHDL designs and ways to make sure that the VHDL designs behave as expected. These techniques include simulation, synthesis of the design to an FPGA or ASIC, and gate-level simulation using VITAL libraries. A new technique called At-Speed Debugging is just becoming available that allows much higher performance verification than a typical simulator, yet provides the design visibility necessary to properly debug a design. This technique provides designers with the ability to debug their design in the target system…
Citation
Douglas L. Perry: VHDL : Programming By Example, Fourth Edition. At Speed Debugging Techniques, Chapter (McGraw-Hill Professional, 2002), AccessEngineering Export